San Francisco, INTI – At the highly anticipated IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry’s Technology Research team showcased a series of groundbreaking advancements in transistor and packaging technologies designed to revolutionize the semiconductor industry. These innovations address the growing demand for high-performance, energy-efficient solutions tailored for artificial intelligence (AI) and next-generation computing applications.
Intel's latest achievements, including advancements in interconnect scaling, heterogeneous integration, and gate-all-around (GAA) transistors, underline its commitment to redefining the semiconductor landscape for the trillion-transistor era.
Pioneering the Path to a New Semiconductor Era
Intel's advancements are driven by the industry's goal to achieve 1 trillion transistors on a single chip by 2030. This ambitious target necessitates breakthroughs across multiple domains, including transistor scaling, advanced packaging, and innovative materials. The developments unveiled at IEDM 2024 are set to not only propel Moore’s Law forward but also redefine the possibilities for AI, computing, and other high-demand technologies.
“Intel Foundry continues to help define and shape the roadmap for the semiconductor industry. Our latest breakthroughs underscore the company’s commitment to delivering cutting-edge technology developed in the U.S., positioning us well to help balance the global supply chain and restore domestic manufacturing and technology leadership with the support of the U.S. CHIPS Act,” said Sanjay Natarajan, Senior Vice President and General Manager of Intel Foundry Technology Research.
Breakthrough Innovations Unveiled
- Subtractive Ruthenium (Ru) for Interconnect Scaling
Intel Foundry introduced subtractive ruthenium, a novel metallization material that significantly enhances interconnect performance. By integrating airgaps with subtractive Ru, Intel achieved up to 25% line-to-line capacitance reduction at pitches below 25 nanometers (nm).
Unlike traditional copper damascene, this process eliminates the need for costly lithographic airgap exclusion zones and self-aligned via flows. The practical, cost-efficient approach is scalable for high-volume manufacturing and sets the stage for the next generation of advanced chip designs.
- Selective Layer Transfer (SLT) for Advanced Packaging
Intel’s Selective Layer Transfer (SLT) technology represents a breakthrough in heterogeneous integration, enabling ultra-fast chip-to-chip assembly with up to 100x higher throughput compared to traditional methods.
SLT supports ultra-thin chiplets with greater flexibility, allowing smaller die sizes, higher aspect ratios, and improved functional density. This innovation offers a cost-effective and adaptable architecture ideal for hybrid and fusion bonding in AI and compute applications.
- Silicon RibbonFET CMOS Transistors
The company showcased its silicon RibbonFET CMOS transistors, achieving a gate length of 6 nm while maintaining industry-leading short-channel effects and performance. This development pushes the boundaries of gate length scaling, a critical component of Moore’s Law, and provides a foundation for continued advancements in transistor miniaturization.
- Gate Oxide for Scaled GAA 2D FETs
To accelerate GAA innovation, Intel presented its work on 2D NMOS and PMOS transistors with gate lengths as small as 30 nm. By focusing on gate oxide module development, the company demonstrated the potential of two-dimensional transition metal dichalcogenide (TMD) semiconductors as a future replacement for silicon in advanced transistor processes.
- Gallium Nitride (GaN) Technology
Intel is pioneering high-performance scaled enhancement-mode GaN MOSHEMTs, fabricated on a 300 mm GaN-on-TRSOI (trap-rich silicon-on-insulator) substrate. This innovation offers improved signal linearity and reduced loss, making it ideal for RF and power electronics applications.
Implications for AI and Beyond
The implications of these innovations extend far beyond traditional computing. Advanced packaging techniques like SLT and interconnect scaling breakthroughs are critical for meeting the growing demands of AI, which require high-performance, energy-efficient solutions capable of handling immense workloads.
Intel Foundry also identified three key innovation pillars to propel the industry toward the trillion-transistor era:
- Advanced memory integration to eliminate bandwidth and latency bottlenecks.
- Hybrid bonding for optimized interconnect bandwidth.
- Modular system expansion with robust connectivity solutions.
Driving Sustainability in Semiconductor Manufacturing
As the industry grapples with thermal and energy constraints, Intel Foundry emphasized the importance of ultra-low voltage transistors capable of operating below 300 millivolts. These advancements promise to dramatically reduce energy consumption and thermal dissipation, paving the way for sustainable semiconductor manufacturing.
The Road Ahead: Collaboration and Innovation
Intel’s groundbreaking developments highlight the necessity of collaboration and innovation to overcome future challenges in semiconductor manufacturing. By redefining the materials, processes, and architectures that underpin chip design, Intel Foundry is ensuring the industry remains on track to meet the ever-growing demand for computing power.
A Vision for the Future
With its innovative approaches to transistor scaling, interconnect design, and packaging, Intel Foundry is setting the stage for a new era of semiconductor technology. These advancements reaffirm Intel's position as a global leader in chip design and manufacturing while addressing the critical challenges of energy efficiency, performance, and scalability in AI and other emerging technologies.
As the world moves closer to the trillion-transistor milestone, Intel’s vision and commitment will continue to shape the future of computing.